https://safirsoft.com AMD shows off stacked 3D V-Cache chiplets, resulting in up to 192MB of L3 cache

AMD caught everyone off guard at Computex 2021 with a demonstration of its new 3D chiplet technology that looks to deliver the type of performance gain you’d typically see with a new process node or microarchitecture.

Developed in collaboration with TSMC, AMD’s first application of the 3D chiplet tech is a vertical cache addition for its high-end processors. In a nutshell, AMD used a process called through-silicon vias (TSVs) to stack additional L3 cache on top of the compute chiplets.

AMD CEO Dr. Lisa Su showed off a prototype Ryzen 5000 CPU with one of two chiplets featuring the added stacked cache. As AnandTech highlights, the difference is obvious compared to the standard chiplet. The 3D V-Cache die is not as large as the core die, so AMD added additional structural silicon for support. Both dies were also thinned, meaning AMD doesn’t have to change up its heatspreader design.

According to AMD, the hybrid bond approach provides "over 200 times the interconnect density of 2D chiplets and more than 15 times the density compared to existing 3D packaging solutions."

AMD highlighted some of the performance gains using a standard Ryzen 9 5900X 12-core processor and one with the 3D V-Cache. The standard processor features 64MB of total L3 cache (32MB per chiplet) while the 3D V-Cache chip boosted this to a total of 192MB. With both CPUs fixed at 4GHz, the system with the new chip exhibited an average of 15 percent better gaming performance at 1080p.

DOTA2 (Vulkan): +18 percent Gears 5 (DX12): +12 percent Monster Hunter World (DX11): +25 percent League of Legends (DX11): +4 percent Fortnite (DX12): +17 percent

AMD said it is on track to begin production of processors with 3D V-Cache chiplets by the end of 2021.

AMD shows off stacked 3D V-Cache chiplets, resulting in up to 192MB of L3 cache
amd-shows-off-stacked-3d-v-cache-chiplets-resulting-in-up.html

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